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DS1381
DS1381 NV RAMport
FEATURES
PIN ASSIGNMENT
TOL PF PI1 PO1 PI2 PO2 PI3 PO3 PI4 PO4 PI5 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC CLK PO8 PI8 NC MEM PO7 PI7 NC PO6 PI6 PO5
* 2K x 8 Nonvolatile Static RAM * 8-Bit transparent I/O Port * Greater than 10 years of data retention in absence of
VCC
* Multiplexed address/data bus reduces pin count * Write protection for both RAM and port status at either
5% or 10%
* Power Fail output signal * Low power CMOS * 24-pin DIP package * Ideally suited for microcontroller applications as add
on memory
24-PIN ENCAPSULATED PACKAGE
PIN DESCRIPTION
PI1 - PI8 PO1 - PO8 PF CLK MEM VCC GND NC - - - - - - - - Port Inputs (P Ports) Port Outputs (External Ports) Power Fail Output Clock Memory Select +5 Volts Ground No Connection
Note: Pins 16 and 20 are missing by design.
DESCRIPTION
The DS1381 is a 2K x 8 nonvolatile static RAM designed to connect directly to the port pins of a microcontroller. Eight of ten port pins required to interface with the microcontroller are reproduced by the DS1381 for general purpose use. The reproduced port pins can be both inputs and outputs and will appear exactly the same as the pins on the attached microcontroller. The static RAM is read or written with three successive cycles containing high order address, low order address and then data. Read, write and status information is passed to the DS1381 along with the high order address transfer. While transferring data to and from memory, the I/O status is locked and maintained. All data within the DS1381 is nonvolatile and data retention time is over 10 years. The DS1381 is controlled by only two signals; clock and memory select.
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DS1381
OPERATION-MEMORY AND PORT PINS
A block diagram of the DS1381 nonvolatile RAMport is shown in Figure 1. As shown, the DS1381 has four key elements; namely the port multiplexer, the RAM interface, a 2K x 8 static RAM, and a power control section. The port multiplexer is connected to eight microcontroller port pins from which address, data and port data are received. The 8 microcontroller port pins are reproduced through transmission gates at the multiplexer output when the MEM pin is high. When the MEM pin is low all reproduced output pins are latched in their high or low states and all reproduced inputs go to a high impedance state. With the MEM pin low the microcontroller port pins are then free to pass address and data to and from the nonvolatile static RAM. Each read or write cycle to memory is accomplished in three separate steps involving two address transfers and one data transfer. The clock signal (CLK) is used to strobe address and data information through the port multiplexer into the RAM interface circuitry. To accomplish RAM access the high order address (A8-A10) is placed on port input pins PI1 through PI3. PI4 through PI8 contain bits which dictate a read of RAM or a write to RAM. If these bits do not match exactly the bit patterns as shown in Figure 2, completion of the full cycle will be allowed but no action will be taken during the data transfer portion. With the proper bit patterns placed on the port pins, the CLK input is then transitioned high to low and then high
again. The clock action allows the address and read/ write information to propagate through the port multiplexer and latch the information into the RAM interface. Next the low order address (A0-A7) is placed on the port input pins (PI1 through PI8) and the second address transfer also propagates through the port multiplexer as CLK goes low and returns high. The RAM is now ready for data transfer. If a write cycle is to occur, the microcontroller port pins must deliver the correct data to be written. As the CLK transitions high to low, data propagates through the port multiplexer and the RAM interface and finally to the RAM where data is written into RAM. The write cycle is terminated when the CLK transitions low to high. Data can then be removed from the port input pins. If during the data transfer a read cycle is to occur, the port input pins must not be driven by the microcontroller. Then as CLK transitions high to low, the RAM becomes active and data is presented on the port input pins for the microcontroller to read. A read cycle is terminated when the CLK signal is transitioned low to high and the port input pins are returned to a high impedance state. After completing the read or write cycle another read or write cycle can be performed without pulsing the MEM pin high between cycles. After all access to the RAM is complete, the MEM pin must be returned to a high state.
FUNCTIONAL BLOCK DIAGRAM Figure 1
CLK
MEM 8 PI1-PI8 P PORTS 8 PORT MULTIPLEXER PO1-PO8 EXTERNAL PORTS ADQ DQ DDR 8 RAM INTERFACE ADD 8 8 ENABLE WRITE 11 2K X 8 RAM
PF
TOL BAT V cc POWER CONTROL VDD
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DS1381
OPERATION - WRITING THE DATA DIRECTION REGISTER
The data direction register is written with a logic one in each bit location which will have a corresponding high impedance output pin (PO1-PO8) during reading and writing of the memory of the DS1381 by the microcontroller (see Figure 3). This will avoid contention between PO1-PO8 and devices driving PO1-PO8 as inputs. To write data to the data direction register, the CLK input is driven low prior to MEM going low. With CLK low MEM is driven low which latches the port output pins and readies the DS1381 for data direction information. Data direction information is then placed on the port input pins by the microcontroller and is written into the data direction register as MEM transitions low to high. While the data direction register is being written, the output pins (PO1 through PO8) are latched to the PI1 through PI8 states with their high or low impedance condition determined by the old data direction contents. The new data direction contents will be effective the next time MEM is taken to a low state.
OPERATION - POWER FAIL AND DATA RETENTION MODE
The DS1381 has full functional capability when Vcc is within normal limits. However, when Vcc goes to an out of tolerance level, the nonvolatile RAMport assumes a write protected status such that the memory and data direction register cannot be accessed. In addition the port output signals go to a high impedance state, the port input pins become "don't care" and the transmission gates connecting the 8 microprocessor port pins to the external ports will go to a low impedance state. The power fail pin (PF) goes to an active low level when power fail occurs and remains low until Vcc returns to nominal limits. The point at which write protection occurs depends on the level of the tolerance pin (TOL). When TOL is grounded, write protection will occur between 4.75 volts and 4.5 volts. When TOL is connected to Vcc, write protection occurs between 4.5 volts and 4.25 volts. After power fail detection has occurred and the Vcc level falls below the voltage level of the internal lithium cell the internal memory and register contents are maintained by this cell which is capable of maintaining data for over 10 years. The switch over from Vcc to the lithium cell occurs when Vcc is below approximately 3 volts.
READ AND WRITE BIT PATTERNS Figure 2
LSB READ A8 A9 A10 1 0 1 0 MSB 1
WRITE
A8
A9
A10
0
1
0
1
0
DATA DIRECTION REGISTER BITS Figure 3
LSB PO1 PO2 PO3 PO4 PO5 PO6 PO7 MSB PO8
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DS1381
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.5V to +7.0V 0C to 70C -40C to +70C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage (TOL=GND) Supply Voltage (TOL=VCC) Logic 1 Input Logic 0 Input SYMBOL VCC VCC VIH VIL MIN 4.75 4.5 2.0 -0.3 TYP 5.0 5.0 MAX 5.5 5.5 VCC + 0.3 +0.8 UNITS V V V V
(0C to 70C)
NOTES 1 1 1 1
DC ELECTRICAL CHARACTERISTICS
PARAMETER Active Current tCYC=200 ns Standby Current Logic 1 Out @ 1 mA Logic 0 Out @ 2 mA VCC Write Protect (TOL=GND) VCC Write Protect (TOL=VCC) Input Leakage Output Leakage Port Pins In to Out Impedance SYMBOL ICC1 ICC2 VOH VOL VTP VTP IIL ILO PZ 2.4
(0C to 70C; VCC within DC operating conditions)
MIN TYP 20 3 MAX 25 7 UNITS mA mA V 0.4 4.50 4.25 -1.0 -1.0 75 4.62 4.37 4.75 4.50 +1.0 +1.0 150 V V V A A NOTES 2 3 1, 6 1, 6 1 1 4 5 7
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT CONDITION tA=25C tA=25C MIN TYP MAX 10 10 UNITS pF pF NOTES
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DS1381
AC ELECTRICAL CHARACTERISTICS
PARAMETER Clock Low Clock High Address Setup Address Hold Data Setup Data Hold MEM to CLK Low MEM to Output Latch CLK to MEM High CLK to Data Valid CLK to Data at High Z CLK to MEM Active DDR Data Setup VCC Slew Rate SYMBOL tCL tCH tAS tAH tDS tDH tMC tML tCMH tCD tDZ tCM tDSD tR, tF 40 100 250 MIN 150 50 20 0 20 0 40 25 10
(0C to 70C TOL = VCC; VCC=4.50 to 5.5V)
TYP MAX UNITS ns ns ns ns ns ns ns ns ns 100 20 ns ns ns ns s NOTES
DATA RETENTION
PARAMETER Expected Data Retention SYMBOL tDR MIN 10 TYP MAX UNITS years
(tA = 25C)
NOTES
NOTES:
1. All voltages are reference to ground 2. Active current is defined as MEM low with CLK low and all outputs are open 3. Standby current is defined as MEM high with CLK high and all outputs are open 4. Input leakage applies to CLK and MEM only 5. Output leakage applies to PF only 6. Logic levels apply to PF and PO1-PO8 when these outputs are latched 7. Port input to output impedance is the on resistance of the transmission gate between port inputs and port outputs with MEM high and with less than 4 mA flowing through the transmission gate.
DC TEST CONDITIONS
Outputs Open All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0V - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ns
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DS1381
TIMING DIAGRAM: WRITE CYCLE TO MEMORY
tCH tCL CLK tMC tML MEM tAS tAH tDS tDH tCMH
PI1-PI8
UPPER ADDRESS VALID
LOWER ADDRESS VALID
DATA IN VALID
PI1-PI8 tML
PORT OUTPUT PINS LATCHED AT THIS TIME PO1-PO8 PORT OUTPUT PINS EQUAL PORT INPUT PINS
TIMING DIAGRAM: READ CYCLE FROM MEMORY
tCH tCL CLK tMC tML tCMH
MEM tAH tCD tDZ
tAS
PI1-PI8
UPPER ADDRESS VALID
LOWER ADDRESS VALID
DATA OUT VALID
PI1-PI8
tML PORT OUTPUT PINS LATCHED AT THIS TIME PO1-PO8 PORT OUTPUT PINS EQUAL PORT INPUT PINS
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DS1381
TIMING DIAGRAM: WRITE CYCLE TO DATA DIRECTION REGISTER
tCL CLK tCM MEM tDH tDSD PI1-PI8 DDR DATA VALID PI1-PI8 tCMH
tML
tML
PORT OUTPUT PINS LATCHED AT THIS TIME PORT OUTPUT PINS EQUAL PORT INPUT PINS
TIMING DIAGRAM: POWER UP - POWER DOWN
VCC 4.75V 4.5V 3.0V 3.0V 4.5V tF tR 4.75V
PF (TOL=GND)
PF (TOL=VCC)
tDR
IL
LEAKAGE CURRENT FROM LITHIUM ENERGY CELL
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DS1381
NONVOLATILE RAMPORT
24 13
1 A
12
C
E
F D K 11 EQUAL SPACES AT .100 .010 TNA G
J H B
DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM
MIN 1.320 33.53 0.675 17.14 0.345 8.76 0.100 2.54 0.015 0.38 0.110 2.79 0.090 2.29 0.590 14.99 0.008 0.20 0.015 0.38
MAX 1.335 33.91 0.700 17.78 0.370 9.40 0.130 3.30 0.035 0.89 0.140 3.57 0.110 2.79 0.630 16.00 0.012 0.30 0.021 0.53
NOTE: PINS 16 AND 20 ARE MISSING BY DESIGN
G IN. MM H IN. MM J IN. MM
K IN. MM
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